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FEATURES
MP7611
Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Parallel Data/Address mP Control Logic
June 1998-3
* Eight Independent Channel 14-Bit DACs with Output Amplifiers * Low Power 320 mW (typ.) * Parallel Digital Data and Address Port * Double Buffered Data Interface * Readback of DAC Latches * Zero Volt Output Preset (Data = 10 .. 00) * 14-Bit Resolution, 12-Bit Accuracy * Extremely Well Matched DACs * Extremely Low Analog Ground Current (<60mA/Channel) * +10 V Output Swing with +11.4 V Supplies
* Rugged Construction -- Latch-Up Free * Serial Version: MP7610 APPLICATIONS * * * * * * *
GENERAL DESCRIPTION
The MP7611 provides eight independent 14-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a parallel digital address and data port.
Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR's patented thin-film resistor process which exhibits excellent long term stability and reliability.
A standard m-processor and TTL/CMOS compatible
ORDERING INFORMATION
Package Type
PQFP PQFP PQFP PLCC PLCC PLCC
m o .c U t4 e e h S ta a .D w w w
Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS
Temperature Range
0 to +70C --40 to +85C --40 to +85C 0 to +70C --40 to +85C --40 to +85C
14-bit input data port loads the data into the pre-selected DACS.
This device can easily be interfaced to a data bus, and digital readback of each channel is available.
Typical DAC matching for C grade versions is 1.5 LSB across all codes. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30ms (typ.).
Part No.
Res. (Bits)
14 14 14 14 14 14
INL (LSB)
|2
MP7611CE MP7611BE MP7611AE MP7611CP MP7611BP MP7611AP
Rev. 3.01
E1998
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
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DNL (LSB)
|2
FSE (LSB)
|16
|4 |8
|3
|24 |32
|4
|2
|2
|16
|4
|3
|24 |32
|8
|4
MP7611
SIMPLIFIED BLOCK DIAGRAM
RB0 D Q LAT0A XRXE XE0 D Q LAT0B XR XE 14
VRP
DAC0
D0 - D13
3
14
Bus I/O
14
VRN
+ --
VO0
A0 - A2 LD1 RD CS R1 R2 LD2
Control Logic
8 8
RB7 XE0 - XE7 RB0 - RB7 D Q LAT7A XR XE XE7 D Q LAT7B XR XE 14
VRP
DAC7
VRN
+ --
VO7
VRP VRP VEE VEE VCC VCC AGND AGND VREF DGND DVDD
-+
VRN
VREFN
PIN CONFIGURATIONS
33 23
1 34 See the following page for pin numbers and descriptions Index 44 12 22
See the following page for pin numbers and descriptions
1
11
44-Pin PQFP (14 mm x 14 mm)
44-Pin PLCC
Rev. 3.01 2
MP7611
PIN OUT DEFINITIONS
PLCC PIN NO. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PQFP PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NAME N/C VO3 VEE VCC N/C VREF VREFN VCC VEE VO4 N/C VO5 VO6 VO7 AGND CS RD R2 R1 LD2 LD1 A2 A1 A0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DVDD DGND AGND VO0 VO1 VO2 DESCRIPTION No Connection DAC 3 Output Analog Negative Power Supply (--12 V) Analog Positive Power Supply (+12 V) No Connection or DVDD Analog Voltage Reference Input (+5 V) Analog Negative Voltage Reference Output (--2.5 V) Analog Positive Power Supply (+12 V) Analog Negative Power Supply (--12 V) DAC 4 Output No Connection DAC 5 Output DAC 6 Output DAC 7 Output Analog Ground ( 0 V) Chip Select Enable Read Back Enable Second--Latch-Bank Reset Enable First--Latch-Bank Reset Enable Second--Latch-Bank Load Enable First--Latch-Bank Load Enable Digital Address Bit 2 Digital Address Bit 1 Digital Address Bit 0 Digital Input Data Bit 0 Digital Input Data Bit 1 Digital Input Data Bit 2 Digital Input Data Bit 3 Digital Input Data Bit 4 Digital Input Data Bit 5 Digital Input Data Bit 6 Digital Input Data Bit 7 Digital Input Data Bit 8 Digital Input Data Bit 9 Digital Input Data Bit 10 Digital Input Data Bit 11 Digital Input Data Bit 12 Digital Input Data Bit 13 (MSB) Digital Positive Power Supply (+5 V) Digital Ground (0 V) Analog Ground (0 V) DAC 0 Output DAC 1 Output DAC 2 Output
Rev. 3.01 3
MP7611
ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = --12 V, VREF = 5 V, DVDD = 5.0 V, T = 25C, Output Load = 5kW (unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B C Differential Non-Linearity A B C Positive Full Scale Error A B C Positive Full Scale Error Temperature Coefficient Negative Full Scale Error A B C Negative Full Scale Error Temperature Coefficient Bipolar Zero Offset A B C Bipolar Zero Offset Temperature Coefficient INL Matching A B C All Channels Maximum Error with DAC 0 adjusted to minimum error A B C Bipolar Zero Matching A B C Full Scale Error Matching A B C N INL |8 |4 |2 DNL |4 |3 |2 +FSE 24 16 12 |32 |24 |16 |32 |24 |16 ppm/C LSB 24 16 12 |32 |24 |16 |32 |24 |16 ppm/C LSB |16 |12 |12 |16 |12 |12 ppm/C LSB |8 |6 |6 ME |8 |6 |6 LSB 0C to 85C 0C to 85C 0C to 85C |4 |3 |2.5 LSB |8 |4 |2.5 LSB 14 Bits LSB End Point Linearity Spec Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
D+FSE/ DT
--FSE
4
D--FSE/ DT
ZOFS
4
DZOFS/ DT DINL
2
|16 |8 |6
|16 |8 |6 LSB |16 |12 |12 LSB |16 |12 |12
DZOFS
|16 |12 |12
DFSE
|16 |12 |12
Rev. 3.01 4
MP7611
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk6 Digital Feedthrough1, 6 Power Supply Rejection Ratio REFERENCE INPUTS Impedance of VREF VREF Voltage1, 2 DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 ANALOG OUTPUTS Output Swing Output Drive Current VREFN Output Drive Current Output Impedance Output Short Circuit Current --VEE +1.4 --5 --10 RO ISC VCC --1.4 5 +10 V mA mA W mA mA mA mA V V 12.75 --5 5.5 10 20 2 420 VREF+1.5 12.75 --12.75 --5 4.5 5.5 10 20 2 450 V V V mA mA mA mW mA VIH VIL IL CL 2.4 0.8 +10 8 V V mA pF REF VREF 350 3.5 700 1.05k 6 350 1.05k W V See Application Hints for driving the reference input tsd CT Q PSRR 30 0.04 --70 5 50 50 ms LSB dB ppm/% ZS to FS (20 V Step) 5k, 50pF load DC CLK and Data to VOUTi DVEE & DVCC = +5%, ppm of FS Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
For test purposes only +FS to AGND +FS to VEE --FS to AGND --FS to VCC
1 25 30 40 55 4.5 0.5
DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time tDS tDH tAS tAH 20 20 100 0 6 0 50 60 60 6 0 ns ns ns ns ns ns ns ns ns ns ns IAGND 60 See Application Notes VIL = 0 V, VIH = 5 V, CL = 20 pF VCC VREF+1.5 12 VEE --12.75 --12 DVDD 4.5 5 ICC 8 IEE 15 IDD PDISS 320 VOH VOL
Bipolar zero Bipolar zero Bipolar zero Bipolar zero
tLD1W tLD1LD2 tLD2W tCS2 tCH2
tCS1 tCH1
Rev. 3.01 5
MP7611
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter DIGITAL TIMING SPECIFICATIONS1, 4 (CONT'D) RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width tRD tDA tDR 600 600 200 100 100 ns ns ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
tR1W tR2W
NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 1, 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < |2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2 VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . --16.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V Analog Outputs & Inputs Infinite Shorts to VCC, VEE, DVDD, AGND and DGND (provided that power dissipation of the package spec is not exceeded) AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for |0.5 V only) Digital Input & Digital Output Voltage to: DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +.5 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . --40C to +85C Military . . . . . . . . . . . . . . . . . . . . . . . . . --55C to +125C Maximum Junction Temperature . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . --65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . +300C Package Power Dissipation Rating to 75C PQFP, PGA, PLCC . . . . . . . . . . . . . . . . . . 800mW Derates above 75C . . . . . . . . . . . . . . . . 11mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms.
APPLICATION NOTES
NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to |300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than |1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths.
Rev. 3.01 6
MP7611
Data Input/Output Bus Address A0-A2 Chip Select CS Load Latch A LD1 Load Latch B LD2 1 0 1 0 1 0 1 0 1 0 +FS --FS tSD don't care tCS1 tLD1W tLD1LD2 tLD2W tAS tAH tCH1 don't care tDS tDH
Analog Output
Figure 1. Loading Latch A and Updating Latch B
Notes: (1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. (3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
Address A0-A2 Chip Select CS Data Readback RD Digital Output Data D0 to D113
1 0 1 0 1 0 1 0 don't care
tAS
tAH
don't care tCS2 tDA tRD tCH2 tDR
HIGH-Z
HIGH-Z
Figure 2. Read Back First Latch Bank of One DAC
Notes: (1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1.
R1 R2
tR1W 1 0 Reset first latch bank to 1000 . . . . .0000 1 0 Reset second latch bank to 1000 . . . . .0000 and analog output to zero volt.
tR2W
Figure 3. Reset Operations
Rev. 3.01 7
MP7611
A standard m-processor and TTL/CMOS compatible input data port loads the data into the pre-selected DACS. If CS = 0, the chip accesses digital data on the bus. Then address bits A0 to A2 select the appropriate DAC and LD1 loads the data into the first-latch-bank. When all 8-channels first-latch-banks are loaded, then LD2 enables the second-latch-bank and updates Function
Load Latch 1 of DAC1 Load Latch 1 of DAC2 Load Latch 1 of DAC3 Load Latch 1 of DAC4 Load Latch 1 of DAC5 Load Latch 1 of DAC6 Load Latch 1 of DAC7 Load Latch 1 of DAC8 Load Latch 2 of DAC1(R)8 Read Latch 1 of DAC1 Read Latch 1 of DAC2 Read Latch 1 of DAC3 Read Latch 1 of DAC4 Read Latch 1 of DAC5 Read Latch 1 of DAC6 Read Latch 1 of DAC7 Read Latch 1 of DAC8 Reset Latch 1 of DAC1(R)8 Reset Latch 2 of DAC1(R)8
all 8-channels simultaneously. The selected DAC becomes transparent (activity on the digital inputs appear at the analog output) when both LD1 = LD2 = 0. R1 = 0 resets the first-latch-bank. R2 = 0 resets the secondlatch-bank which sets the analog output to zero volts (data = 100...00), regardless of digital inputs. RD
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X X
A2
0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X X
A1
0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X X
A0
0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X X
LD1
0(R)1 0(R)1 0(R)1 0(R)1 0(R)1 0(R)1 0(R)1 0(R)1 1 1 1 1 1 1 1 1 1 X X
LD2
1 1 1 1 1 1 1 1 0(R)1 1 1 1 1 1 1 1 1 X X
CS
0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 X X
R1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
R2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Note: 1: High, 0: Low, X: Don't Care
Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table
Note: For timing information see Electrical Characteristics
Rev. 3.01 8
MP7611
A0 to A2 3 3-8 Decoder 8 8 To first latch bank enable
LD1 8 CS RD LD2 R1 R2 To second latch bank enable To reset all first latch bank To reset all second latch bank 8 To switches across the first latch bank for readback enable
Figure 4. Simplified Parallel Logic Port
Hex Code OOOO
Binary Code 00000000000000
Output Voltage = 2 * Vr (--1 + 2*D ) (Vr = +5 V) 16384 10 * (--1 + 0) = --10
1FFF 2OOO 2OO1
01111111111111 10000000000000 10000000000001
10 * (--1 +
16382 ) = --1.22 mV 16384 16384
10 * (--1 +16384 ) = 0 10 * (--1 +16386 ) = 1.22 mV 16384
3FFF
11111111111111
10 * (--1 +32766 ) = 9.99878
16384
Table 2. MP7611 Ideal DAC Output vs. Input Code
Note: See Electrical Characteristics for real system accuracy
Rev. 3.01 9
MP7611
16 3 AS Address Decoder A0 to A2
A0 to A15
mP
R From System Reset
LD1
R1 R2
DB0 to DB16
From System Reset
12 or 14
DB0 to DB11 or DB13
Figure 5. Parallel mP Interface
Rev. 3.01 10
MP7611
PERFORMANCE CHARACTERISTICS
11 V
0V
--11 V 2.5mV
VOUT
0V
--2.5mV VOUT Settling 50ms/Division
Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF
Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output.
4
14-BIT LSB --4 0
CODE
16384
Graph 2. Linearity with VREF = 5 V, All DACs, All Codes
Rev. 3.01 11
MP7611
Graph 3. DAC 0 INL vs. VREF
4 4
Graph 4. DAC 0 DNL vs. VREF
14-BIT LSB
--4
14-BIT LSB --4 0
0
CODE
16384
CODE
16384
Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = |10
4 4
Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = |9
14-BIT LSB
--4
0
CODE
16384
14-BIT LSB --4 0
CODE
16384
Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = |8
Rev. 3.01 12
Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = |7
MP7611
VOUT MP7610 Family
50
VO I
5k
500pF
CL
2mA
CL = 500pF, 5nF, 50nF, 500nF
Figure 6. Circuit for Determining Typical Analog Output Pulse Response
2.0mA
I
0.0 400mV
VO
--400mV 200mV CL = 500pF CL = 5nF
CL = 50nF
CL = 500nF
VOUT
--200mV 0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See Figure 9. above)
Rev. 3.01 13
MP7611
44 LEAD PLASTIC QUAD FLAT PACK (14 mm x 14 mm QFP)
Rev. 1.00
D D1 33 23
34
22
D1 D
44
12
1 A2 A Seating Plane A1 B e
11
C
a
L
INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.110 0.010 0.100 0.014 0.005 0.667 0.547 0.026 0 MAX 0.134 0.014 0.120 0.020 0.009 0.687 0.555 0.37 7
MILLIMETERS MIN 2.80 0.25 2.55 0.35 0.13 16.95 13.90 0.65 0 MAX 3.40 0.35 3.05 0.50 0.23 17.45 14.10 0.95 7
0.039 BSC
1.00 BSC
a
Note: The control dimension is the millimeter column
Rev. 3.01 14
MP7611
44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
D D1 2 1 44 45 x H2 45 x H1
C
Seating Plane A2
B1
D
D1
D3
BD 2
e
D3 A1 A INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.685 0.650 0.590 MAX 0.180 0.120 ------. 0.021 0.032 0.013 0.695 0.656 0.630 MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 17.40 16.51 14.99 MAX 4.57 3.05 -----0.53 0.81 0.32 17.65 16.66 16.00
R
0.500 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
12.70 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
Note: The control dimension is the inch column
Rev. 3.01 15
MP7611
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.01 16

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